The present invention relates to a method for manufacturing a small-sized semiconductor device typified by a wafer level CSP (Chip Scale Package) formed by dividing a semiconductor wafer into each fraction, and a semiconductor device.
There has recently been an increasingly demand for miniaturization and thinning of a semiconductor device having an internal circuit in which a plurality of semiconductor elements are brought into integration. As to the semiconductor device that needs to make its thinning in particular, a CSP-type semiconductor device in which spherical bump electrodes each connected to an internal circuit thereof are disposed in grid or lattice form, is in the mainstream.
In a method for manufacturing such a CSP-type conventional semiconductor device, an internal circuit is formed on the front surface of a semiconductor substrate of a semiconductor wafer. Each electrode pad electrically connected to the internal circuit is provided on an insulating layer formed on the front surface. After a surface protective film has covered over the electrode pad and the insulating layer, the surface protective film provided on the electrode pad is removed by etching to form an insulating film made of polyimide on the surface protective film. A through hole that reaches the electrode pad is formed by etching the insulating film.
A bedding metal layer is formed on the electrode pad and the insulating film by a sputtering method. With a resist mask formed by photolithography as a mask, an about 5 μm-thick redistribution wiring made of copper (Cu), which extends from above the electrode pad to above a post-electrode forming electrode forming area, is formed on the bedding metal layer by an electroplating method. Each post electrode of about 100 μm is formed of copper or the like by the electroplating method using a resist mask thick in thickness, which has exposed the electrode forming area lying on the corresponding redistribution wiring. The bedding metal layer excluding below each redistribution wiring is removed by wet etching. Thereafter, the corresponding semiconductor wafer is inserted into an encapsulation mold and a sealing resin such as an epoxy resin is injected to the entire surface on the front surface side of the semiconductor substrate to form a sealing layer. A post end surface of each post electrode is exposed to its front surface. The semiconductor wafer in which each of hemispherical bump electrodes is formed on the post end surface, is divided into each fraction, whereby the corresponding semiconductor device is manufactured (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2003-60120 (mainly paragraph 0047 in the 6th page—paragraph 0066 in the 7th page, and FIGS. 7 through 10)).
Since the thick resist mask for forming each post electrode in the patent document 1 has a maximum thickness equivalent to a thickness of 30 μm or in the case of a liquid resist, a resist mask forming process step is required plural times. With this view, it has been generally practiced to attach a dry film having photosensitivity and subject it to exposure and development by photolithography thereby to expose the electrode forming area lying on the corresponding redistribution wiring.
When a powerful solvent is used to remove the attached dry film, an influence exerted on the environment occurs. Therefore, if a removal solvent friendly to the environment is used, then dry-film residues occur in the neighborhood of a base of each post electrode and between the adjacent redistribution wirings, thereby causing a short circuit due to a failure in etching of the bedding metal layer at a bedding metal layer etching step, whereby the reliability of the semiconductor device might be degraded.
In order to eliminate the film residues in such a conventional semiconductor device manufacturing method, a dry film is attached onto the corresponding bedding metal layer inclusive of each redistribution wiring after the formation of the redistribution wiring in a manner similar to the above. The electrode forming area lying on the redistribution wiring is exposed by photolithography. Each post electrode is formed by copper or the like according to an electroplating method, and the dry film is peeled off by a resist peeling liquid. Thereafter, steam of 120° C. or higher is sprayed onto the semiconductor wafer thereby to eliminate the film residues that remain on then outer peripheral surface of the base of the post electrode and a connecting pad at its periphery (refer to, for example, a patent document 2 (Japanese Unexamined Patent Publication No. 2004-281614 (mainly paragraphs 0010-0017 in the 3rd page and FIG. 4).
With the recent miniaturization of the semiconductor device, miniaturization has been promoted even in the case of the CSP-type semiconductor device. Redistribution wrings for connecting between bump electrodes disposed in grid form and electrode pads each electrically connected to a predetermined portion of an internal circuit while being shifted, have been brought into micro-fabrication, and the wiring-interval narrowing of making the interval between the adjacent redistribution wirings narrower has been performed.
The technology of the above patent document 2, however, needs to introduce new cleaning equipment for injecting high-temperature steam because the steam of 120° C. or higher is sprayed onto the semiconductor wafer to eliminate the film residues. Thus, a problem arises in that heavy burdens such as equipment costs therefor, a change in production line and the like occur.
Since the steam of 120° C. or higher is sprayed onto the semiconductor wafer to eliminate the film residues that remain on the outer peripheral surface of the base of each post electrode and the connecting pad at its periphery, there is a case in which when the wiring interval between the redistribution wirings is narrow, e.g., 30 μm or less, it is difficult to eliminate the film residues mechanically sandwiched between the redistribution wirings. Thus, a problem arises in that there is a fear that a short circuit produced by the bedding metal layer having remained due to a failure in etching of the bedding metal layer due to the film residues occurs and the reliability of the semiconductor device is hence degraded.
This is especially prominent in the semiconductor device having the redistribution wirings narrowed in wiring interval.